SART-OB: Addestramento Residuale Safety-Aware con Vincoli Operativi per il Controllo Real-Time della Frequenza in Reti Elettriche a Bassa Inerzia

Abstract

I risultati mostrano che SART-OB raggiunge un'accuratezza media molto vicina a quella dell'MPC, ma con una minore attività media del comando e senza richiedere la risoluzione online di un problema di ottimizzazione. Infine, ho caratterizzato l'implementazione su Jetson Orin, verificando che i tempi di esecuzione sono ampiamente compatibili con il periodo di controllo considerato. La validazione delle prestazioni è stata svolta in simulazione, mentre come sviluppo futuro è prevista una validazione Hardware-in-the-Loop completa.

This thesis addresses the problem of active power control in low-inertia power systems, where the increasing penetration of inverter-based renewable energy sources makes frequency regulation more challenging due to faster frequency dynamics. The objective of this work is to develop and validate a novel control framework, called SART-OB (Safety-Aware Residual Training with Operating Bounds), which combines Reinforcement Learning with deterministic industrial control strategies. The proposed framework adopts a residual architecture in which a PPO-based policy does not replace the conventional controller but learns only a limited corrective action. Safety is ensured through Operating Bounds that enforce actuator saturation, rate limiting and finite-state-machine supervision. The proposed approach is compared with both a conventional controller and a Model Predictive Controller under three deterministic scenarios and a balanced Monte Carlo campaign of one hundred simulations. The results show that SART-OB achieves an average Mean Absolute Error close to that of MPC while providing a lower average command activity, without requiring the online solution of an optimization problem at every control step. Finally, the framework is characterized on an NVIDIA Jetson Orin platform, demonstrating that its execution time is fully compatible with the considered control period. Control performance is validated in simulation, while future work will focus on complete Hardware-in-the-Loop validation and integration with physical I/O.